1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a process of deposition, heat treatment or the like that is carried out, under the condition that the substrate temperature is 600 to 770.degree. C. after formation of a gate electrode over a gate oxide film with a film thickness of 3 nm or less.
2. Description of the Related Art
Referring to FIGS. 4 to 6, a conventional method of manufacturing a filed effect transistor is described.
First, after an element isolation region 2 is formed on the surface of a semiconductor substrate 1, a gate oxide film 3 (3 nm in thickness) is formed on the semiconductor substrate 1 by the thermal oxidation method and then polysilicon 4 (150 nm in thickness) is formed thereon. Next, over the polysilicon 4, a photoresist (not shown in the drawings) is applied and, using this as a mask, the polysilicon 4 and the gate oxide film 3 are patterned into the shape of a gate electrode. Following that, BF.sub.2 implantation is carried out over the entire surface to form a SD (source-drain) extension region 5. The condition for the BF.sub.2 implantation is, for example, that an accelerating energy is 5 keV and a dose is 2.times.10.sup.14 cm.sup.-2 or so. Thereafter, a sidewall 6 and a through oxide film 7 are formed and the structure shown in FIG. 4(a) is obtained.
Next, by applying another ion implantation through a through oxide film 7 over the entire surface, doping into the gate electrode and formation of a source-drain region 8 are carried out (FIG. 4(b)). The condition for this boron implantation is, for example, that an accelerating energy is 4 keV and a dose is 3.times.10.sup.15 cm.sup.-2 or so.
Subsequently, a lamp anneal is performed so as to bring about the activation within the gate electrode and the source-drain region. The condition for the lamp anneal is normally that the substrate temperature is 900 to 1000.degree. C. and the annealing time is 5-10 seconds (FIG. 4(c)).
After the lamp anneal, cobalt 9 (20 nm is thickness) is deposited over the entire surface (FIG. 4(d)).
Next, a heat treatment is applied thereto in nitrogen atmosphere at 600 to 700.degree. C. for 10 seconds and, then, after removing the superfluous cobalt, another anneal is performed in nitrogen atmosphere at 800.degree. C. for 10 seconds, and thereby cobalt 9 is turned to silicide 91 (FIG. 5(e)). Turning to silicide, cobalt 9 with a film thickness of 10 nm becomes cobalt silicide 91 with a film thickness of 30-40 nm. The formation of cobalt silicide facilitates to lower the resistance of the gate electrode and the contact resistance of the diffusion layers. A silicon nitride film 10 (50 nm in thickness) is then formed over the entire surface by the low-pressure thermal CVD (Chemical Vapor Deposition) method (FIG. 5(f)). The deposition temperature is set to be a 600 to 750.degree. C. and the deposition time, 3-4 hours. The low-pressure thermal CVD method is employed therein, since a silicon nitride film formed by this method serves well as an etching stopper. Furthermore, if the plasma CVD method is used, for example, it may cause adverse effects such as dielectric breakdown or the like on the gate oxide film.
Next, over the entire surface of the substrate, an interlayer film 11 (1000 nm in thickness) made of BPSG (Boro-Phospho-Silicate Glass) is formed by the plasma CVD method (FIG. 5(g)). The deposition temperature for that is 400.degree. C. or so.
After that, a photoresist 13 is applied to the entire surface of the interlayer film 11 but an opening left at a prescribed position, and, then, by performing dry etching, a contact hole 12 is formed (FIG. 6(h)). As the etching gas, a gas having a high etching selectivity of BPSG to silicon nitride is used. After the silicon nitride film is exposed at the bottom of the contact hole 12, this silicon nitride film is subjected to another dry etching, with a CHF.sub.3 -based gas being used as the etching gas. This leads to the exposure of cobalt silicide at the bottom of the contact hole 12 (FIG. 6(i)).
After that, a barrier metal film made of Ti/TiN is formed around the inside wall of the contact hole and, by filling that with tungsten or the like, a contact plug is formed.
In the method described above, the silicon nitride film 10 is formed as shown in FIG. 5(f). Without this silicon nitride film 10, the leakage of the current may occur through overetching, if the position of the contact opening is slipped as shown in FIG. 9. A slight shift in alignment is a problem that can happen easily during the manufacturing process so that measures to cope with such a problem is a matter of importance. In the method described above, the silicon nitride film 10 serves as an etching stopper in forming the contact hole 12, and thereby a problem of the current leakage is eliminated.
Next, referring to the drawings, a conventional method of manufacturing a DRAM (Dynamic Random Access Memory) is described.
First, in the same way as the afore-mentioned conventional method of a field effect transistor, the steps shown in FIGS. 4-6 are performed. Next, after a Ti/TiN film 20 is formed inside of the contact hole as a barrier metal by the sputtering method, the hole is buried with tungsten 21 by the thermal CVD method with the deposition temperature set at 400.degree. C. or so. The subsequent planarization of the surface by the CMP method brings the structure shown in FIG. 11(a).
A lower capacitor-electrode layer 31 (100 nm in thickness) composed of Ti, TiN and Pt is then formed over the entire surface by the sputtering method. Over this, a PZT (PbZr.sub.x Ti.sub.1-x O.sub.3) film 32 is also formed by the sputtering method (FIG. 11(b)). These sputterings are carried out, for example, under the condition that the substrate temperature is 650 to 750.degree. C. and the sputtering time is 10-60 minutes or so.
Next, an upper capacitor-electrode layer 33 made of lrO.sub.2 /Ir is formed over the entire surface by the sputtering method (FIG. 12(a)). After that, the lower capacitor-electrode layer 31, the PZT film 32 and the upper capacitor-electrode layer 33 are patterned by dry etching, and thereby a PZT capacitor 30 is formed (FIG. 12(b)).
With both conventional techniques described above, however, problems of increasing the resistance of the gate electrode and deteriorating the element response arise.
The present inventors made an investigation to elucidate causes of such problems and found out that they are caused by the gate depletion in the vicinity of the gate oxide film resulting from the deactivation of dopants which takes place in the step of forming a silicon nitride film 10 shown in FIG. 5(f).
This point is described below in detail, taking the case of the afore-mentioned conventional method of manufacturing a field effect transistor. In this manufacturing method, the lamp anneal performed at 900 to 1000.degree. C. for 10 seconds or so in the step of FIG. 4(c) brings about the activation within the gate electrode and the source-drain region 8. The silicon nitride film 10 is then formed, by the low-pressure thermal CVD method, setting the deposition temperature at 600 to 750.degree. C., in the later step of FIG. 5(f). A heat treatment conducted in this temperature range, however, causes the deactivation of dopants and, as a result, the dopant concentration decreases. In other words, even if a certain activation of dopants is once achieved by a heat treatment performed in the later step at a temperature as low as 600 to 750.degree. C. as described above, the activation of dopants settles down at a lower activation yield corresponding to this lower temperature.
Now, when the field effect transistor is in use, an application of a voltage to the gate electrode makes the depletion layer spread in the upper section of the gate oxide film. Moreover, the lower the dopant activation yield within the gate electrode is, the more this depletion layer spreads. Therefore, in the afore-mentioned conventional technique, a lowering of the dopant activation yield results in an expansion of the depletion layer, which gives rise to problems of increasing in the resistance of the gate electrode and deteriorating the element response.
Further, also in the afore-manufactured method of manufacturing a DRAM, while the lamp anneal is performed at 900 to 1000.degree. C. for 10 seconds or so in the step of FIG. 4(c), the sputtering is carried out at 650 to 750.degree. C., in the later step of FIG. 11(b), in forming the PZT film 32. This causes the deactivation of dopants and lowers the dopant concentration, which gives rise, as above, to the problems of increasing the resistance of the gate electrode and deteriorating the element response.
Meanwhile such problems accompanied with a lowering of the dopant activation yield as described above become more notable with the reduction of the film thickness of the gate oxide film. Especially in the case that the film thickness of the oxide film is 3 nm or less, the problems become very serious. When doped polysilicon is used as a constitutive material of the gate electrode, the depletion layer spreads in the gate electrode. The thickness of this depletion layer depends on the dopant concentration. The ratio of the capacitance of the depletion layer to the gate capacitance generally increases, as the gate oxide film becomes thinner. The close examination by the present inventors, however, showed that the effects of the depletion layer on the characteristics of transistors described above become strongly marked only when the gate oxide film becomes as thin as 3 nm or thinner so that this film thickness of 3 nm can be the critical point.
To satisfy recent demands that the miniaturization of elements is achieved, that is, 0.1 .mu.m-level minute devices are realized, it is necessary that the film thickness of the gate oxide film is set to be 3 nm or less. Accordingly, an object of the present invention is to overcome problems arising specifically for the case that such a film thickness is set for the gate oxide film, namely, problems accompanied with the lowering of the dopant activation yield in a gate electrode as described above.